Copyright 1999 IEEE, Proceedings of DCC'99, Snowbird, March 1999

A fractional Chip Wavelet Zero Tree Codec (WZT) for video compression

Krasimir Kolarov, William Lynch, Bill Arrighi, Bob Hoover

Interval Research Corporation, 1801-C Page Mill Road, Palo Alto, CA 94304

*(**kolarov@interval.com** , **lynch@interval.com**)*

We are introducing a motion Wavelet transform Zero Tree (WZT) codec which achieves good compression ratios and can be implemented in a single ASIC of modest size (and very low cost). The codec employs a group of pictures (GOP) of two interlaced video frames, edge filters for the boundaries, intermediate field image compression and block compression structure. Specific features of the implementation for a small single chip are:

- Transform filters are short and use dyadic rational coefficients with small numerators. Implementation can be accomplished with adds and shifts. We propose a Mallat pyramid resulting from five filter applications in the horizontal direction and three applications in the vertical direction for each (30x23=240)x(20x25=640) field. This produces filters with dyadic coefficients, two coefficients in the low pass filter and two, four, or six coefficients in the wavelet filters (resulting in 12 wavelet sub-bands). We use modified edge filters near block and image boundaries so as to utilize actual image values.

- Motion image compression is used in place of motion compensation. We have applied transform compression in the temporal direction to a GOP of four fields. A two level temporal Mallat pyramid is used as a tensor product with the spatial pyramid. The linear edge filters are used at the fine level and the modified Haar filters at the coarse level, resulting in four temporal subbands. Each of these temporal subbands is formed into a zero-tree and compressed.

- Processing can be decoupled into the processing of blocks of 8 scan lines of 32 pixels each. This helps reduce the RAM requirements to the point that the RAM can be placed in the ASIC itself. This reduces the chip count and also simplifies the satisfaction of RAM bandwidth requirements. WZT processing is performed stripe by stripe (two passes per stripe).

- Quantization denominators are powers of two, enabling implementation by shifts.

- Zero-Tree coding yields a progressive (i.e., embedded) encoding which is easily rate controlled. Inspired by the SPIHT algorithm, we have designed a tree walking procedure particularly appropriate for hardware implementation.

- The codec itself imposes a very low delay of less than 3.5 ms within a field and 67 ms. for a GOP. A reasonable estimate for the hardware required to implement this with a slow clock rate of 1 clock per pixel time is 40 Kgates, equivalent to less than the space required for 1 million bits. The overall conclusion is that it is reasonable to expect that this method can be implemented, including memory, in a few mm^{2} of silicon.

The technical innovations that enable the above features are:

- Edge filters which enable blockwise processing while preserving quadratic continuity across block boundaries, greatly reducing blocking artifacts.

- Field image compression reduces memory requirements for fields within a GOP.

Our simulations demonstrate significantly better performance of WZT with respect to Analog Devices' ADV601. In the experiments WZT outperforms ADV601 significantly in speed and quality (both perceptually and in PSNR by 1-2.3db) for a variety of test sequences (talk show, panning fence, zooming bridge, basketball game).